This invention relates generally to computers and more particularly to a computer main memory that uses a data strobe protocol to transfer data between the computer""s main memory and controller.
A computer""s main memory is comprised of numerous individual memory units such as Dynamic Random Access Memory units (DRAM)s for the storage of data. In such computers data is typically transferred into and out of the individual DRAMs to the controller in accordance with a predefined clocking scheme. For example, transferring data into and out of the DRAMs to a data controller, i.e., writing or reading, typically includes the steps of generating a suitable data signal that is sent from the controller to one or more selected DRAMs and then either writing data, from the controller, into the selected DRAMs or reading data out of the selected DRAMs and returning the data to the controller.
Today, improved DRAMs are of the class of Double Data Rate DRAMs presently referred to, in the industry, as DDR devices.
These Double Data Rate DRAMs use a data and strobe protocol to transfer the data between the memory and the controller. The period of time in which a data word can be transferred into or out of the computer""s memory, i.e., written or read, is equal to one half of one cycle of the memory system clock. When reading data from a DDR device, the device drives both the data bus and the strobe simultaneously. The strobe must be toggled for each data word read from the DDR until all the data are the read out because the controller uses it to latch the incoming data word until the read is complete. The strobe is edges aligned, meaning that it transitions coincident with the data. Therefore, the controller receiving the data must phase shift the strobe in order to use it to latch the incoming data word.
When writing to a DDR device, the controller drives the data bus with the strobe centered with respect to the data, meaning that the strobe transitions in the middle of the data valid time. The controller toggles the strobe for each data word sent to the DDR device receiving the data thus the DDR device only needs to use the strobe to latch the incoming data word.
The period of time when all of the data inputs are valid at either the controller on a data read or the DDR devices on a data write is known as the xe2x80x9cdata eyexe2x80x9d. As the memory clock frequencies in computers continue to increase, the duration of this data eye gets shorter and the relationship between the strobe and data eye becomes tighter causing the aligning of these independent signals, i.e., the strobe and data eye, to become increasingly difficult because of the time variations caused by simultaneous switching outputs, noise on reference voltages, path lengths and propagation delay mismatches, crosstalk, and other such effects.
Thus the current protocol for DDR devices is to toggle the strobe with every read/write data transfer and have timing restraints on the strobe and data transfer times and as frequencies go higher these restraints on strobe and data become so stringent that a limit is quickly reached and data can no longer be transferred into or out of the DDR devices.
Therefore the currently used protocol has a problem in aligning the data strobe with the data eye as the data rates keep increasing and with faster data rates this alignment problem becomes more severe. This problem thus prevents the DDR devices from being used at their full potential.
The invention permits a relaxing of the strobe to data eye relationship for reads and writes so that DDR devices can be used at their full potential. The present invention thus permits the use of higher frequency memory clocks which results in smaller data eyes and higher data rates.
The present invention allows all DDR devices to be used to their fullest by relaxing the timing requirements required for aligning the strobe with each data eye. In the present invention, this is accomplished by having the data self-latch when there is a transition in the data word. A data word is the summation of all of the data bits transferred from or to a DDR device on a single clock edge. A transition is any change in a bit in the data such as a change from a xe2x80x9c1xe2x80x9d to a xe2x80x9c0xe2x80x9d or vice versa. This self latching procedure means that the strobe need only be used in those cases where there is no change in the data word.
In this way, the present invention can relax the strobe to data eye alignment problem found in the prior art protocol, the use of smaller data eyes resulting higher data transfer rates.
The present invention accomplishes these desirable results by altering the prior art DDR write and read circuits as well as the memory controller write and read circuits. More particularly, the prior art DDR device write circuit and controller read circuits are modified by adding a strobe generator and coupling this generator to both the strobe and the data inputs. The DDR device read circuitry and the controller write circuitry is modified to include a data compare circuit controlling both the output latch and chip driver circuitry with some initialize and enable circuitry. These changes permit the present invention to be self-latching based on data transitions and eliminates the use of the data strobe except when there are no data transitions.
Therefore it is an object of the present invention to eliminate strobe to data relationships for reads and writes except when there are no data transitions.
It is a further object of the invention to eliminate strobe to data eye alignment when data is changing to permit the data eye to be smaller and increase data transfer rates in the computer.
These objects, features and advantages of the present invention will be become further apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings wherein:.